The present invention relates to a method for patterning metal layers in integrated circuits.
A problem area of particular importance is the fabrication of VLSI structures having more than two levels of wiring. The additional design flexibility offered by a technology which includes three levels of wiring (such as polysilicon plus two levels of metal, or two levels of polysilicon plus metal) is extremely convenient in designing complex random logic, such as microprocessors, and can not only reduce required design time, but also raise the available performance of resulting circuits, since faster routings, avoiding propagation delays, can often be used. However, in such a multi-level structure, the vertical topographical excursion of the upper levels becomes quite large. This can impose considerable difficulties in step coverage, since the vertical height which may be exposed to the step may be very large. Moreover, this vertical excursion may cause disastrous focusing problems, since the vertical excursion of the uppermost metal layer may exceed the depth of field of normal projection exposure systems.
Thus, it would be highly desirable to have a convenient method for patterning small-geometry metal contacts, vias, and wiring lines.
It is an object of the present invention to provide a method for patterning metal films in integrated circuits at small geometries.
It is a further object of the present invention to provide a method for patterning metal films in integrated circuits which can cover very large vertical steps.
A method which has been previously proposed to accomplish these first two objectives is lift-off patterning. In the conventional methods, a patterned resist layer is applied, a metal film is deposited overall, and the resist is then removed with solvent. This requires a relatively long resist removal step, and the separation of the metal at the edges of the pattern resist is tricky. Moreover, extremely good control of the resist job is required. Efforts have been made to achieve the necessary resist control by using double resist techniques, but these lead to additional process complexity and are not yet proven. For further background on prior art lift-off techniques, see generally Semiconductor International, Dec. 1981, pp. 72-88.
It is an object of the present invention to provide a lift-off technique which does not require extremely precise control of resist sidewall profiles.
It is a further object of the present invention to provide a lift-off technique which does not require multi-level resist technology.
It is a further object of the present invention to provide a lift-off technique which does not remove the patterned resist layer.
It is a further object of the present invention to provide a lift-off technique which does not require introduction of solvent to cause an underlying resist layer to swell.
It is a further object of the present invention to provide a lift-off technique which reliably separates the metal at the edges of the patterned resist layer.
It is a further object of the present invention to provide a method for patterning metals, such as tungsten which are difficult to etch selectively.
It is a further object of the present invention to provide a method for patterning high-thermal-conductivity materials other than metals.
It is a further object of the present invention to provide a method for patterning silicides.
It is a further object of the present invention to provide a method for selectively removing portions of a uniform silicide layer, on an integrated circuit.
It is a further object of the present invention to provide a method for selectively depositing silicides over high-thermal-conductivity areas of an integrated circuit without any selective etching step.
It is a further object of the present invention to provide a method for selectively depositing silicides over high thermal-conductivity areas of an integrated circuit without any etching step.